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Part Number 405GPr Revision 2.04 - September 7, 2007
405GPr
Power PC 405GPr Embedded Processor
Features
* PowerPC(R) 405 32-bit RISC processor core operating up to 400MHz with 16KB I- and D-caches * Synchronous DRAM (SDRAM) interface operating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications * 4KB on-chip memory (OCM) * External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported * DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels * PCI Revision 2.2 compliant interface (32-bit, up to 66MHz)
Data Sheet
- Synchronous or asynchronous PCI Bus interface - Internal or external PCI Bus Arbiter * Ethernet 10/100Mbps (full-duplex) support with media independent interface (MII) * Programmable interrupt controller supports 13 external and 19 internal edge triggered or levelsensitive interrupts * Programmable timers * Two serial ports (16550 compatible UART) * One IIC interface * General purpose I/O (GPIO) available * Supports JTAG for board level testing * Internal processor local Bus (PLB) runs at SDRAM interface frequency * Supports PowerPC processor boot from PCI memory * Unique software-accessible 64-bit chip ID number (ECID).
Description
Designed specifically to address embedded applications, the PowerPC 405GPr (PPC405GPr) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: CMOS SA-27E, 0.18 m (0.11 m Leff) Package: 456-ball (35mm or 27mm) enhanced plastic ball grid array (E-PBGA) in both leaded and lead-free versions Power (typical): 0.72W at 266MHz
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405GPr - Power PC 405GPr Embedded Processor
Revision 2.04 - September 7, 2007
Data Sheet
Contents
Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 On-Chip Memory (OCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PLB to PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10/100 Mbps Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Signal List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Tables
System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O Specifications--Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O Specifications--Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PPC405GPr Legacy Mode Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PPC405GPr New Mode Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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405GPr - Power PC 405GPr Embedded Processor
Data Sheet
Figures
PPC405GPr Embedded Controller Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 27mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5V-Tolerant Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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405GPr - Power PC 405GPr Embedded Processor
Revision 2.04 - September 7, 2007
Data Sheet
Ordering, PVR, and JTAG Information
Processor Frequency 266MHz 266MHz 266MHz 266MHz 266MHz 266MHz 266MHz 266MHz 333MHz2 333MHz2 333MHz2 333MHz2 333MHz2 333MHz2 333MHz2 333MHz2 400MHz 400MHz 400MHz 400MHz 400MHz 400MHz 400MHz 400MHz Rev Level B B B B B B B B B B B B B B B B B B B B B B B B
Product Name PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr PPC405GPr
Order Part Number1 PPC405GPr-3BB266 PPC405GPr-3JB266 PPC405GPr-3BB266Z PPC405GPr-3JB266Z PPC405GPr-3DB266 PPC405GPr-3KB266 PPC405GPr-3DB266Z PPC405GPr-3KB266Z PPC405GPr-3BB333 PPC405GPr-3JB333 PPC405GPr-3BB333Z PPC405GPr-3JB333Z PPC405GPr-3DB333 PPC405GPr-3KB333 PPC405GPr-3DB333Z PPC405GPr-3KB333Z PPC405GPR-3BB400 PPC405GPr-3JB400 PPC405GPR-3BB400Z PPC405GPr-3JB400Z PPC405GPr-3DB400 PPC405GPr-3KB400 PPC405GPr-3DB400Z PPC405GPr-3KB400Z
Package 35mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 35mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA 27mm, 456 E-PBGA
PVR Value 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951 0x50910951
JTAG ID 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049 0x24088049
Notes 1: Z at the end of the Order Part Number indicates a tape-and-reel shipping package. Otherwise, the chips are shipped in a tray. 2. If the 333MHz parts are operated at 266MHz or less, the operational temperature range is extended to 105C
The part number contains a revision code. This refers to the die mask revision number and is included in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) is software accessible and contains additional information about the revision level of the part. Refer to the PowerPC 405GPr Embedded Processor User's Manual for details on the register content.
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Data Sheet
Order Part Number Key
PPC405GPr-3BB266x
Shipping Package Blank = Tray Z = Tape and reel Part Number Grade 3 Reliability Processor Speed 266MHz 333MHz 400MHz Revision Level
Package and Operational Case Temperature B: 35mm, 456 E-PBGA, -40C to +85C D: 27mm, 456 E-PBGA, -40C to +85C J: 35mm, 456 E-PBGA lead-free, -40C to +85C K: 27mm, 456 E-PBGA lead-free, -40C to +85C
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Data Sheet
PPC405GPr Embedded Controller Functional Block Diagram
Universal Interrupt Controller Clock Control Reset Timers MMU Power Mgmt DOCM IOCM OCM SRAM DCRs OCM Control GPIO IIC UART UART
PPC405 Processor Core JTAG 16KB D-Cache DCU Trace ICU
DCR Bus
16KB I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA Controller (4-Channel)
OPB Bridge
MAL
Ethernet
Arb Code Decompression (CodePackTM)
Processor Local Bus (PLB)
SDRAM Controller
External Bus Controller
External Bus Master Controller
PCI Bridge
13-bit addr 32-bit data
32-bit addr 32-bit data
66 MHz max (async) 33 MHz max (sync)
MII
The PPC405GPr is designed using the IBM(R) Microelectronics Blue LogicTM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnectTM Bus Architecture.
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405GPr - Power PC 405GPr Embedded Processor
Data Sheet
Address Map Support
The PPC405GPr incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC405GPr processor through the use of mtdcr and mfdcr instructions.
System Memory Address Map 4GB System Memory
Function Subfunction SDRAM, External Peripherals, and PCI Memory Note: Any of the address ranges listed at right may be use for any of the above functions. Peripheral Bus Boot 1 PCI Boot PCI I/O PCI I/O PCI Configuration Registers Interrupt Acknowledge and Special Cycle Local Configuration Registers UART0 UART1 Internal Peripherals IIC0 OPB Arbiter GPIO Controller Registers Ethernet Controller Registers
2
Start Address 0x00000000 0xE8010000 0xEC000000 0xEEE00000 0xEF500000 0xF0000000 0xFFE00000 0xFFFE0000 0xE8000000 0xE8800000 0xEEC00000 0xEED00000 0xEF400000 0xEF600300 0xEF600400 0xEF600500 0xEF600600 0xEF600700 0xEF600800
End Address 0xE7FFFFFF 0xE87FFFFF 0xEEBFFFFF 0xEF3FFFFF 0xEF5FFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xE800FFFF 0xEBFFFFFF 0xEEC00007 0xEED00003 0xEF40003F 0xEF600307 0xEF600407 0xEF60051F 0xEF60063F 0xEF60077F 0xEF6008FF
Size 3712MB 8MB 44MB 6MB 1MB 256MB 2MB 128KB 64KB 56MB 8B 4B 64B 8B 8B 32B 64B 128B 256B
General Use
Boot-up
Notes: 1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above. 3. After the boot process, software may reassign the boot memory regions for other uses. 4. All address ranges not listed above are reserved.
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Data Sheet
DCR Address Map 4KB Device Configuration Registers
Function Total DCR Address Space1 By function: Reserved Memory Controller Registers External Bus Controller Registers Decompression Controller Registers Reserved On-Chip Memory Controller Registers Reserved PLB Registers Reserved OPB Bridge Out Registers Electronic Chip ID (ECID) Reserved Clock, Control, Interrupt Routing, and Reset Power Management Interrupt Controller Reserved DMA Controller Registers Reserved Ethernet MAL Registers Reserved Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB). 0x000 0x010 0x012 0x014 0x016 0x018 0x020 0x080 0x090 0x0A0 0x0A8 0x0AA 0x0B0 0x0B8 0x0C0 0x0D0 0x100 0x140 0x180 0x200 0x00F 0x011 0x013 0x015 0x017 0x01F 0x07F 0x08F 0x09F 0x0A7 0x0A9 0x0AF 0x0B7 0x0BF 0x0CF 0x0FF 0x13F 0x17F 0x1FF 0x3FF 16W 2W 2W 2W 2W 8W 96W 16W 16W 8W 2W 6W 8W 8W 16W 48W 64W 64W 128W 512W Start Address 0x000 End Address 0x3FF Size 1KW (4KB)1
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Data Sheet
On-Chip Memory (OCM)
The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: * Low-latency access to critical instructions and data * Performance identical to cache hits without misses * Contents change only under program control
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor and local memory. This interface is compliant with version 2.2 of the PCI Specification. Features include: * Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is optional and can be disabled for systems which employ an external arbiter. * PCI bus frequency up to 66MHz - Synchronous operation at 1/n fractions of PLB speed (n = 1 to 4) to 33MHz maximum - Asynchronous operation from 1/8 PLB frequency to 66MHz maximum * 32-bit PCI address/data bus * Power Management: - PCI Bus Power Management v1.1 compliant * Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI * Buffering between PLB and PCI: - PCI target 64-byte write post buffer - PCI target 96-byte read prefetch buffer - PLB slave 32-byte write post buffer - PLB slave 64-byte read prefetch buffer * Error tracking/status * Supports PCI target side configuration * Supports processor access to all PCI address spaces: - Single-byte PCI I/O reads and writes - PCI memory single-beat and prefetch-burst reads and single-beat writes - Single-byte PCI configuration reads and writes (type 0 and type 1) - PCI interrupt acknowledge - PCI special cycle
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Data Sheet
* Supports PCI target access to all PLB address spaces * Supports PowerPC processor boot from PCI memory
SDRAM Memory Controller
The PPC405GPr Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to four physical banks. Up to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: * 11x8 to 13x11 addressing for SDRAM (2- and 4-bank) * 32-bit memory interface support * Programmable address compare for each bank of memory * Industry standard 168-pin DIMMS are supported (some configurations) * PC-133 support for 133 MHz memory * 4MB to 256MB per bank * Programmable address mapping and timing * Auto refresh * Page mode accesses with up to 4 open pages * Power management (self-refresh) * Error checking and correction (ECC) support - Standard single-error correct, double-error detect coverage - Aligned nibble error detect - Address error logging
External Peripheral Bus Controller (EBC)
* Supports eight banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals * Up to 66MHz operation * Burst and non-burst devices * 8-, 16-, 32-bit byte-addressable data bus width support * Latch data on Ready * Programmable 2K clock time-out counter with disable for Ready * Programmable access timing per device - 0-255 wait states for non-bursting devices - 0-31 burst wait states for first access and up to 7 wait states for subsequent accesses
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Data Sheet
- Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS * Programmable address mapping * Peripheral Device pacing with external "Ready" * External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for own access and control
DMA Controller
* Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers * Four channels * Scatter/gather capability for programming multiple DMA operations * 8-, 16-, 32-bit peripheral support (OPB and external) * 32-bit addressing * Address increment or decrement * Internal 32-byte data buffering capability * Supports internal and external peripherals * Support for memory mapped peripherals * Support for peripherals running on slower frequency buses
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Data Sheet
Serial Interface
* One 8-pin UART and one 4-pin UART interface provided * Selectable internal or external serial clock to allow a wide range of baud rates * Register compatibility with NS16550 register set * Complete status reporting capability * Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode * Fully programmable serial-interface characteristics * Supports DMA using internal DMA engine
IIC Bus Interface
* Compliant with Philips(R) Semiconductors I2C Specification, dated 1995 * Operation at 100kHz or 400kHz * 8-bit data * 10- or 7-bit address * Slave transmitter and receiver * Master transmitter and receiver * Multiple bus masters * Supports fixed VDD IIC interface * Two independent 4 x 1 byte data buffers * Fifteen memory-mapped, fully programmable configuration registers * One programmable interrupt request signal * Provides full management of all IIC bus protocol * Programmable error recovery
General Purpose IO (GPIO) Controller
* Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses * 23 of 24 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with: - 7 of 8 chip selects - All 13 external interrupts - All nine instruction trace pins * Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, threestated if output bit is 1)
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405GPr - Power PC 405GPr Embedded Processor
Data Sheet
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: * Supports 13 external and 19 internal interrupts * Seven of the 13 interrupts are mapped to the same GPIOs as the PPC405GP. * The other six interrupts can be mapped to any of the GPIOs. * Edge triggered or level-sensitive * Positive or negative active * Non-critical or critical interrupt to processor core * Programmable critical interrupt priority ordering * Programmable critical interrupt vector for faster vector processing
10/100 Mbps Ethernet MAC
* Capable of handling full/half duplex 100Mbps and 10Mbps operation * Uses the medium independent interface (MII) to the physical layer (PHY not included on chip)
JTAG
* IEEE 1149.1 test access port * IBM RISCWatch debugger support * JTAG Boundary Scan Description Language (BSDL)
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Data Sheet
27mm, 456-Ball E-PBGA Package
Top View
Part Number
Logo View
Gold Gate Release Corresponds to A1 Ball Location
(R)
24 TYP
PPC405GPr
1YWWBZZZZZ CCCCCCC
Notes: 1. All dimensions are in mm.
2. This package is available in leaded or lead-free configurations.
Lot Number
C 0.20 C 0.25 C 0.35 C
0.20 27.0 25.0
A
Bottom View
AF AD AB Y V T 27.0 P M K H F D
AE AC AA W U R N L J G E Thermal Balls
1.0 TYP
Mold Compound
PCB Substrate
C B A 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 0.60 0.1 SOLDERBALL x 456 0.30 M C A B 0.10 M C 0.50.1 2.65 max
B
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405GPr - Power PC 405GPr Embedded Processor
Data Sheet
35mm, 456-Ball E-PBGA Package
Top View
Part Number
Logo View
Gold Gate Release Corresponds to A1 Ball Location
(R)
30.0 Typ
PPC405GPr
1YWWBZZZZZ CCCCCCC
Notes: 1. All dimensions are in mm.
2. This package is available in leaded or lead-free configurations.
Lot Number
C 0.20 C 0.25 C 0.35 C
0.20 35.0 31.75
A
Bottom View
AF AD AB Y V T 35.0 P M K H F D
AE AC AA W U R N L J G E Thermal Balls
1.27
Mold Compound
PCB Substrate
C B A 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 0.75 0.15 SOLDERBALL x 456 0.30 M C A B 0.15 M C 0.60.1 2.65 max
B
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Data Sheet
Pin Lists
The PPC405GPr embedded controller is available as a 456-ball E-PBGA leaded or lead-free package. The 456ball package is available in two sizes--35 millimeters and 27 millimeters. In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear. The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list--once for each signal name on the ball. The page number listed gives the page in "Signal Functional Description" on page 30 where the signals in the indicated interface group begin.
Signals Listed Alphabetically
Signal Name AGND AVDD BA0 BA1 BankSel0 BankSel1 BankSel2 BankSel3 BE0[PCIC0] BE1[PCIC1] BE2[PCIC2] BE3[PCIC3] BusReq CAS ClkEn0 ClkEn1 DMAAck0 DMAAck1 DMAAck2 DMAAck3 DMAReq0 DMAReq1 DMAReq2 DMAReq3 DQM0 DQM1 DQM2 DQM3 DQMCB ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 EMCMDClk EMCMDIO[PHYMDIO] EMCTxD0 EMCTxD1 EMCTxD2 EMCTxD3 EMCTxEn Ball E22 D25 AB24 AC24 AD17 AF17 AE15 AC14 D19 F24 K24 R26 R3 AB23 AB25 AC25 D16 B15 B14 C12 C16 D14 C11 A7 AC12 AC10 AC6 AA3 AC15 AE14 AF15 AF14 AD13 AF13 AF12 AE13 AD12 H24 AD26 J26 L25 L24 P25 K23
(Sheet 1 of 9)
Interface Group Page 35 35 32
System System SDRAM
SDRAM
32
PCI External Master Peripheral SDRAM SDRAM
30 34 32 32
External Slave Peripheral
32
External Slave Peripheral
32
SDRAM SDRAM
32 32
SDRAM
32
Ethernet Ethernet Ethernet Ethernet
31 31 31 31
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Data Sheet
Signals Listed Alphabetically
Signal Name EMCTxErr EOT0/TC0 EOT1/TC1 EOT2/TC2 EOT3/TC3 ExtAck ExtReq ExtReset Ball K25 F3 G2 V2 Y1 Y3 Y4 T3 Ethernet External Slave Peripheral External Master Peripheral External Master Peripheral External Master Peripheral
(Sheet 2 of 9)
Interface Group Page 31 32 34 34 34
GND
A1 A2 A6 A11 A16 A19 A21 A26 B2 B25 B26 C3 C24 D4 D23 E5 E9 E13 E14 E18 F1 Ground F26 Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also H1 thermal balls. J5 J22 L1 L11-L16 L26 M11-M16 N5 N11-N16 N22 P5 P11-P16 P22 R11-R16 T1 T11-T16 T26 V5 V22 W26 AA1 AA26 AB5
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Data Sheet
Signals Listed Alphabetically
Signal Name Ball AB9 AB13 AB14 AB18 AB22 AC4 AC23 AD3 AD24 AE1 AE2 AE25 AF1 AF6 AF8 AF11 AF16 AF21 AF25 AF26 C19 D18 C20 A22 AF18 AC9 AE8 AF5 AC7 AB3 C4 C5 A4 B9 B10 A9 B11 V25 V23 W24 W25 Y24 Y25 AA24 D20 AB26 U2 T2 V1 AD6 AE7 V25 V23 W24 W25 Y24 Y25 AA24
(Sheet 3 of 9)
Interface Group Page
GND
Ground Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also thermal balls.
37
Gnt[PCIReq0] GPIO1[TS1E] GPIO2[TS2E] GPIO3[TS1O] GPIO4[TS2O] GPIO5[TS3] GPIO6[TS4] GPIO7[TS5] GPIO8[TS6] GPIO9[TrcClk] [GPIO10]PerCS1 [GPIO11]PerCS2 [GPIO12]PerCS3 [GPIO13]PerCS4 [GPIO14]PerCS5 [GPIO15]PerCS6 [GPIO16]PerCS7 [GPIO17]IRQ0 [GPIO18]IRQ1 [GPIO19]IRQ2 [GPIO20]IRQ3 [GPIO21]IRQ4 [GPIO22]IRQ5 [GPIO23]IRQ6 GPIO24 Halt HoldAck HoldPri HoldReq IICSCL IICSDA IRQ0[GPIO17] IRQ1[GPIO18] IRQ2[GPIO19] IRQ3[GPIO20] IRQ4[GPIO21] IRQ5[GPIO22] IRQ6[GPIO23]
PCI
30
System
35
System
35
System
35
System External Master Peripheral External Master Peripheral External Master Peripheral Internal Peripheral Internal Peripheral
35 34 34 34 34 34
Interrupts
35
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Data Sheet
Signals Listed Alphabetically
Signal Name MemAddr0 MemAddr1 MemAddr2 MemAddr3 MemAddr4 MemAddr5 MemAddr6 MemAddr7 MemAddr8 MemAddr9 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 MemData0 MemData1 MemData2 MemData3 MemData4 MemData5 MemData6 MemData7 MemData8 MemData9 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AE22 AC21 AE21 AD21 AF22 AE20 AC19 AE19 AD19 AC18 AF19 AD18 AC17 AC26 AA23 AC13 AE12 AD11 AC11 AF10 AE11 AD10 AF9 AD9 AE9 AD8 AF7 AC8 AD7 AE6 AE5 AE4 AD5 AD4 AC5 AD1 AB2 AA4 AA2 AB1 Y2 W4 W2 W3 V4 W1 V3
(Sheet 4 of 9)
Interface Group Page
SDRAM Note: During a CAS cycle MemAddr0 is the least significant bit (lsb) on this bus.
32
SDRAM
32
SDRAM Note: MemData0 is the most significant bit (msb) on this bus.
32
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Data Sheet
Signals Listed Alphabetically
Signal Name Ball B17 C13 E6 E7 E8 E19 E20 E21 F5 F22 G5 G22 H5 H22 K2 N24 P3 U25 W5 W22 Y5 Y22 AA5 AA22 AB6 AB7 AB8 AB19 AB20 AB21 AD14 AE10 A17 B16 C17 A18 D17 C18 B18 A20 B21 A23 D21 B22 B23 C22 C26 F25 K26 L23 M25 M23 N25 M26 N26 P24 R24 R23 P23 R25 T24 U26 T25 V26 D19 F24 K24 R26
(Sheet 5 of 9)
Interface Group Page
OVDD
Output driver voltage
37
PCIAD0 PCIAD1 PCIAD2 PCIAD3 PCIAD4 PCIAD5 PCIAD6 PCIAD7 PCIAD8 PCIAD9 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0[BE0] PCIC1[BE1] PCIC2[BE2] PCIC3[BE3]
PCI Note: PCIAD31 is the most significant bit (msb) on this bus.
30
PCI
30
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Data Sheet
Signals Listed Alphabetically
Signal Name PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY PerAddr0 PerAddr1 PerAddr2 PerAddr3 PerAddr4 PerAddr5 PerAddr6 PerAddr7 PerAddr8 PerAddr9 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk Ball B20 H25 J24 U23 T23 F23 H26 N23 M24 P26 C23 J23 E26 G25 C19 C21 B19 A24 G23 J25 B24 G24 H23 G26 D5 A3 B4 B5 D6 B6 C6 D7 A5 B7 C7 D8 B8 C8 D9 A8 C9 D10 C10 A10 D11 B12 D13 D12 B13 A12 A13 C14 A14 A15 C15 D15 F2 E4 PCI PCI PCI
(Sheet 6 of 9)
Interface Group Page 30 30 30
PCI
30
PCI PCI PCI PCI PCI
30 30 30 30 30
PCI
30
PCI PCI PCI PCI
30 30 30 30
External Slave Peripheral
32
External Slave Peripheral External Master Peripheral
32 34
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Data Sheet
Signals Listed Alphabetically
Signal Name PerCS0 PerCS1[GPIO10] PerCS2[GPIO11] PerCS3[GPIO12] PerCS4[GPIO13] PerCS5[GPIO14] PerCS6[GPIO15] PerCS7[GPIO16] PerData0 PerData1 PerData2 PerData3 PerData4 PerData5 PerData6 PerData7 PerData8 PerData9 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16 PerData17 PerData18 PerData19 PerData20 PerData21 PerData22 PerData23 PerData24 PerData25 PerData26 PerData27 PerData28 PerData29 PerData30 PerData31 PerErr PerOE PerPar0 PerPar1 PerPar2 PerPar3 PerReady PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 [PerWE]PCIINT PHYCol PHYCrS PHYRxClk PHYMDIO[EMCMDIO] PHYRxD0 PHYRxD1 PHYRxD2 PHYRxD3 PHYRxDV Ball B3 C4 C5 A4 B9 B10 A9 B11 U4 U3 U1 T4 R2 P4 R4 P2 R1 P1 N3 N1 M1 N2 M3 M4 N4 M2 L3 L4 K1 L2 K3 J1 K4 J3 J2 J4 H3 G1 H2 H4 B1 C2 D3 G4 G3 E1 E3 C1 D2 E2 F4 D1 C23 AA25 W23 AF20 AD26 AE23 AF23 AC20 AD20 V24
(Sheet 7 of 9)
Interface Group Page
External Slave Peripheral
32
External Slave Peripheral
32
External Master Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral External Slave Peripheral Ethernet Ethernet Ethernet Ethernet Ethernet Ethernet
34 32 32 32 32 32 32 31 31 31 31 31 31
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Data Sheet
Signals Listed Alphabetically
Signal Name PHYRxErr PHYTxClk RAS Ball U24 E25 AF24 C25 E23 E24 Y23 Y26 AF41 U23 A25 AD25 D22 AD22 AE24 AD23 D26 D24 AC22 AE26 D18 C20 A22 AF18 AC9 AE8 AF5 AC7 AB3 AB4 AE18 AE3 AF2 AD15 AD16 AE16 AF3 AC3 AC3 AD2 AD2 AC1 AC2 AE17 Ethernet Ethernet SDRAM Other Note: AF4 must be tied to OVDD or GND. All other reserved pins should be left unconnected. PCI System System System JTAG JTAG JTAG System System JTAG JTAG
(Sheet 8 of 9)
Interface Group Page 31 31 32
Reserved
37
Req[PCIGnt0] SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk TMS TRST [TS1E]GPIO1 [TS2E]GPIO2 [TS1O]GPIO3 [TS2O]GPIO4 [TS3]GPIO5 [TS4]GPIO6 [TS5]GPIO7 [TS6]GPIO8 [TrcClk]GPIO9 UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_CTS/UART1_DSR UART1_DSR/UART1_CTS UART1_DTR/UART1_RTS UART1_RTS/UART1_DTR UART1_Rx UART1_Tx UARTSerClk
30 35 35 35 35 35 35 35 35 35 35
System
35
Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral Internal Peripheral
34 34 34 34 34 34 34 34 34 34 34 34 34 34 34
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Data Sheet
Signals Listed Alphabetically
Signal Name Ball E10 E11 E12 E15 E16 E17 K5 K22 L5 L22 M5 M22 R5 R22 T5 T22 U5 U22 AB10 AB11 AB12 AB15 AB16 AB17 AC16
(Sheet 9 of 9)
Interface Group Page
VDD
Logic voltage
37
WE
SDRAM
32
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Data Sheet
Signals Listed by Ball Assignment
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 H23 H24 H25 H26 Signal Name GND GND PerAddr1 PerCS3[GPIO12] PerAddr8 GND DMAReq3 PerAddr15 PerCS6[GPIO15] PerAddr19 GND PerAddr25 PerAddr26 PerAddr28 PerAddr29 GND PCIAD0 PCIAD3 GND PCIAD7 GND GPIO3[TS1O] PCIAD9 PCIReq3 SysClk GND PerErr GND PerCS0 PerAddr2 PerAddr3 PerAddr5 PerAddr9 PerAddr12 PerCS4[GPIO13] PerCS5[GPIO14] PerCS7[GPIO16] PerAddr21 PerAddr24 PCIStop EMCMDClk PCIDevSel PCIGnt3 Ball B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 M1 M2 M3 M4
(Sheet 1 of 3)
Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 P14 P15 P16 P22 Signal Name PerWBE3 PerWBE0 PerPar0 GND PerAddr0 PerAddr4 PerAddr7 PerAddr11 PerAddr14 PerAddr17 PerAddr20 PerAddr23 PerAddr22 DMAReq1 PerAddr31 DMAAck0 PCIAD4 GPIO1[TS1E] PCIC0[BE0] GPIO24 PCIAD10 SysReset GND TmrClk AVDD TestEn PerPar3 PerWBE1 PerReady PerClk GND OVDD OVDD OVDD GND VDD VDD VDD GND GND GND GND GND Ball E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 U1 U2 U3 U4 Signal Name GND VDD VDD VDD GND OVDD OVDD OVDD AGND Reserved Reserved PHYTxClk PCIParity GND PerBLast EOT0/TC0 PerWBE2 OVDD OVDD PCIGnt2 PCIC1[BE1] PCIAD15 GND PerData29 EOT1/TC1 PerPar2 PerPar1 OVDD OVDD PCIReq4 PCISErr PCIPErr PCITRDY GND PerData30 PerData28 PerData31 OVDD OVDD PerData2 HoldAck PerData1 PerData0
Signal Name DMAAck2 DMAAck1 PCIAD1 OVDD PCIAD6 PCIReq2 PCIClk PCIAD8 PCIAD11 PCIAD12 PCIReset GND GND PerR/W PerOE GND PerCS1[GPIO10] PerCS2[GPIO11] PerAddr6 PerAddr10 PerAddr13 PerAddr16 PerAddr18 DMAReq2 DMAAck3 OVDD PerAddr27 PerAddr30 DMAReq0 PCIAD2 PCIAD5 PCIReq0[Gnt] GPIO2[TS2E] PCIReq1 PCIAD13 PCIINT[PerWE] GND Reserved PCIAD14 PerData12 PerData17 PerData14 PerData15
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Data Sheet
Signals Listed by Ball Assignment
Ball J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L11 L12 L13 L14 L15 L16 L22 L23 L24 L25 L26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 AA24 Signal Name PerData23 PerData26 PerData25 PerData27 GND GND PCIIRDY PCIFrame PCIReq5 EMCTxD0 PerData20 OVDD PerData22 PerData24 VDD VDD EMCTxEn PCIC2[BE2] EMCTxErr PCIAD16 GND PerData21 PerData18 PerData19 VDD GND GND GND GND GND GND VDD PCIAD17 EMCTxD2 EMCTxD1 GND GND MemData23 DQM3 MemData22 OVDD OVDD MemClkOut1 IRQ6[GPIO23] Ball M5 M11 M12 M13 M14 M15 M16 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N11 N12 N13 N14 N15 N16 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P11 P12 P13 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7
(Sheet 2 of 3)
Ball P23 P24 P25 P26 R1 R2 R3 R4 R5 R11 R12 R13 R14 R15 R16 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T11 T12 T13 T14 T15 T16 T22 T23 T24 T25 T26 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 Signal Name PCIAD26 PCIAD23 EMCTxD3 PCIIDSel PerData8 PerData4 BusReq PerData6 VDD GND GND GND GND GND GND VDD PCIAD25 PCIAD24 PCIAD27 PCIC3[BE3] GND HoldPri ExtReset PerData3 VDD GND GND GND GND GND GND VDD PCIGnt1 PCIAD28 PCIAD30 GND MemData8 MemData6 MemData2 ECC7 ECC3 OVDD UART0_RI UART0_RTS Ball U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 Signal Name VDD VDD PCIGnt0[Req] PHYRxErr OVDD PCIAD29 HoldReq EOT2/TC2 MemData31 MemData29 GND GND IRQ1[GPIO18] PHYRxDV IRQ0[GPIO17] PCIAD31 MemData30 MemData27 MemData28 MemData26 OVDD OVDD PHYCrS IRQ2[GPIO19] IRQ3[GPIO20] GND EOT3/TC3 MemData25 ExtAck ExtReq OVDD OVDD Reserved IRQ4[GPIO21] IRQ5[GPIO22] Reserved UART0_DCD MemAddr7 MemAddr5 MemAddr2 MemAddr0 PHYRxD0 TDI GND VDD GND GND GND GND GND GND VDD
Signal Name
PCIAD19 PCIGnt5 PCIAD18 PCIAD21 PerData11 PerData13 PerData10 PerData16 GND GND GND GND GND GND GND GND PCIGnt4 OVDD PCIAD20 PCIAD22 PerData9 PerData7 OVDD PerData5 GND GND GND GND Halt UART1_Rx UART1_Tx UART1_DSR/ UART1_CTS GND MemData19 DQM2 GPIO8[TS6]
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Data Sheet
Signals Listed by Ball Assignment
Ball AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 Signal Name PHYCol GND MemData24 MemData21 GPIO9[TrcClk] UART0_CTS GND OVDD OVDD OVDD GND VDD VDD VDD GND GND VDD VDD VDD GND OVDD OVDD OVDD GND CAS BA0 ClkEn0 Ball AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
(Sheet 3 of 3)
Ball AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 Signal Name BankSel0 MemAddr11 MemAddr8 PHYRxD3 MemAddr3 TCK TDO GND SysErr EMCMDIO [PHYMDIO] GND GND UART0_DSR MemData16 MemData15 MemData14 IICSDA GPIO6[TS4] MemData9 OVDD MemData5 MemData1 ECC6 ECC0 BankSel2 UART0_Rx UARTSerClk Ball AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal Name TRST GND UART0_DTR UART0_Tx Reserved GPIO7[TS5] GND MemData11 GND MemData7 MemData4 GND ECC5 ECC4 ECC2 ECC1 GND BankSel1 GPIO4[TS2O] MemAddr10 PHYRxClk GND MemAddr4 PHYRxD1 RAS GND GND
Signal Name MemData12 GPIO5[TS3] DQM1 MemData3 DQM0 MemData0 BankSel3 DQMCB WE MemAddr12 MemAddr9 MemAddr6 PHYRxD2 MemAddr1 TMS GND BA1 ClkEn1 MemClkOut0 MemData20 UART1_RTS/ UART1_DTR GND MemData18 MemData17 IICSCL MemData13 MemData10
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Data Sheet
Signal List
The following table provides a summary of the number of package pins associated with each functional interface group.
Pin Summary
Group
PCI Ethernet SDRAM External peripheral External master Internal peripheral Interrupts JTAG System Total Signal Pins OVDD VDD Gnd Thermal (and Gnd) Reserved Total Pins
No. of Pins
60 18 71 96 9 15 7 5 18 299 32 24 59 36 6 456
Multiplexed Pins In the table "Signal Functional Description" on page 30, each external signal is listed along with a description of the signal function. Some signals are multiplexed on the same pin (ball) so that the pin can be used for different functions. Multiplexed signals are shown as a default signal with a secondary signal in square brackets (for example, GPIO1[TS1E]). Active-low signals (for example, RAS) are marked with an overline. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. In addition to multiplexing, many pins are also multi-purpose. For example, the EBC peripheral controller address pins are used as outputs by the PPC405GPr to broadcast an address to external slave devices when the PPC405GPr has control of the external bus. When, during the course of normal chip operation, an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC405GPr. In this example, the pins are also bidirectional, serving as both inputs and outputs. Intialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Strapping" on page 51). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable.
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Data Sheet
Pull-Up and Pull-Down Resistors Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3k to +3.3V (10k to +5V can be used on 5V tolerant I/Os) and pull-down value of 1k to GND, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or GND. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405GPr. Unused I/Os For some interfaces, it is possible to turn off input receivers for some or all of the signals by means of bit settings in register CPC0_CR1. When this gating capability is applied to unused signals, it is not necessary to terminate them. Refer to the PowerPC 405GPr Embedded Processor User's Manual for details. If receiver gating is not used, termination of some pins may be necessary when they are unused. Although the PPC405GPr requires only the pull-up and pull-down terminations as specified in the "Signal Functional Description" on page 30, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, and receiver gating is not used, the peripheral, SDRAM, and PCI buses should be configured and terminated as follows: * Peripheral interface--PerAddr0:31, PerData0:31, and all of the control signals are driven by default. Terminate PerReady high and PerError low. * SDRAM--Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405GPr to actively drive all of the SDRAM address, data, and control signals. * PCI--The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and actively drive PCIAD31:0, PCIC3:0[BE3:0], and the remaining PCI control signals by doing the following: - Strap the PPC405GPr to disable the internal PCI arbiter and to operate the PCI interface in synchronous mode. - Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3k resistors to +3.3V. - Terminate PCIReq1:5 to +3.3V. - Terminate PCIReq0[Gnt] to GND. External Bus Control Signals All peripheral bus control signals (PerCS0:7, PerR/W, PerWBE0:3, PerOE, PerWE, PerBLast, HoldAck, ExtAck) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC 405GPr Embedded Processor User's Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions and/or when an external master owns the peripheral bus. As a result, a pullup resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405GPr. Please refer to "Signals Listed Alphabetically" on page 16 for the pin number to which each signal is assigned.
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Data Sheet
Signal Functional Description
(Sheet 1 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description I/O Type
Notes
PCI Interface
PCIAD31:0 PCIC3:0[BE3:0] PCI Address/Data Bus. Multiplexed address and data bus. PCI bus command and byte enables. PCI parity. Parity is even across PCIAD0:31 and PCIC0:3[BE0:3]. PCIParity is valid one cycle after either an address or data phase. The PCI device that drove PCIAD0:31 is responsible for driving PCIParity on the next PCI bus clock. PCIFrame is driven by the current PCI bus master to indicate the beginning and duration of a PCI access. PCIIRDY is driven by the current PCI bus master. Assertion of PCIIRDY indicates that the PCI initiator is ready to transfer data. The target of the current PCI transaction drives PCITRDY. Assertion of PCITRDY indicates that the PCI target is ready to transfer data. The target of the current PCI transaction can assert PCIStop to indicate to the requesting PCI master that it wants to end the current transaction. PCIDevSel is driven by the target of the current PCI transaction. A PCI target asserts PCIDevSel when it has decoded an address and command encoding and claims the transaction. PCIIDSel is used during configuration cycles to select the PCI slave interface for configuration. PCISErr is used for reporting address parity errors or catastrophic failures detected by a PCI target. PCIPErr is used for reporting data parity errors on PCI transactions. PCIPErr is driven active by the device receiving PCIAD0:31, PCIC0:3[BE0:3], and PCIParity, two PCI clocks following the data in which bad parity is detected. PCIClk is used as the asynchronous PCI clock when in asynchronous mode. It is unused when the PCI interface is operated synchronously with the PLB bus. PCI specific reset. PCI interrupt. Open-drain output (two states; 0 or open circuit) or Peripheral write enable. Low when any of the four PerWBE0:3 write byte enables are low. Multipurpose signal, used as PCIReq0 when internal arbiter is used, and as Gnt when external arbiter is used. Used as PCIReq1:5 input when internal arbiter is used. I/O I/O 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 2
PCIParity
I/O
PCIFrame PCIIRDY PCITRDY
I/O I/O I/O
2 2 2
PCIStop
I/O
2
PCIDevSel
I/O
2
PCIIDSel PCISErr
I I/O
PCIPErr
I/O
2
PCIClk
I
5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI
PCIReset
O
PCIINT[PerWE]
O
PCIReq0[Gnt] PCIReq1:5
I I
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Revision 2.04 - September 7, 2007
405GPr - Power PC 405GPr Embedded Processor
Data Sheet
Signal Functional Description
(Sheet 2 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name PCIGnt0[Req] Description Gnt0 when internal arbiter is used or Req when external arbiter is used. Used as PCIGnt1:5 output when internal arbiter is used. I/O O Type 5V tolerant 3.3V PCI 5V tolerant 3.3V PCI
Notes
PCIGnt1:5
O
Ethernet Interface
PHYRxD3:0 EMCTxD3:0 PHYRxErr PHYRxClk Received data. This is a nibble wide bus from the PHY. The data is synchronous with the PHYRxClk. Transmit data. A nibble wide data bus towards the net. The data is synchronous to the PHYTxClk. Receive Error. This signal comes from the PHY and is synchronous to the PHYRxClk. Receiver Medium clock. This signal is generated by the PHY. Receive Data Valid. Data on the Data Bus is valid when this signal is activated. Deassertion of this signal indicates end of the frame reception. Carrier Sense signal from the PHY. This is an asynchronous signal. Transmit Error. This signal is generated by the Ethernet controller, is connected to the PHY and is synchronous with the PHYTxClk. It informs the PHY that an error was detected. Transmit Enable. This signal is driven by the EMAC to the PHY. Data is valid during the active state of this signal. Deassertion of this signal indicates end of frame transmission. This signal is synchronous to the PHYTxClk. This clock comes from the PHY and is the Medium Transmit clock. Collision signal from the PHY. This is an asynchronous signal. Management Data Clock. The MDClk is sourced to the PHY. This clock has a period of 400ns, adjustable via EMAC0_STACR[OPBC]. Management information is transferred synchronously with respect to this clock. Management Data Input/Output is a bidirectional signal between the Ethernet controller and the PHY. It is used to transfer control and status information. I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1 6 1 1
PHYRxDV
I
1
PHYCrS
I
1
EMCTxErr
O
6
EMCTxEn
O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
6
PHYTxClk PHYCol
I I
1 1
EMCMDClk
O
EMCMDIO[PHYMDIO]
I/O
5V tolerant 3.3V LVTTL
1
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405GPr - Power PC 405GPr Embedded Processor
Revision 2.04 - September 7, 2007
Data Sheet
Signal Functional Description
(Sheet 3 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description I/O Type
Notes
SDRAM Interface
Memory data bus. Notes: 1. MemData0 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb). Memory address bus. Notes: 1. MemAddr12 is the most significant bit (msb). 2. MemAddr0 is the least significant bit (lsb). Bank Address supporting up to 4 internal banks. Row Address Strobe. Column Address Strobe. DQM for byte lane: 0 (MemData0:7), 1 (MemData8:15), 2 (MemData16:23), and 3 (MemData24:31) DQM for ECC check bits. ECC check bits 0:7. Select up to four external SDRAM banks. Write Enable. SDRAM Clock Enable. Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer.
MemData0:31
I/O
3.3V LVTTL
MemAddr12:0
O
3.3V LVTTL
BA1:0 RAS CAS
O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
DQM0:3
O
3.3V LVTTL
DQMCB ECC0:7 BankSel0:3 WE ClkEn0:1 MemClkOut0:1
O I/O O O O O
3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL
External Slave Peripheral Interface
PerData0:31 Peripheral data bus used by PPC405GPr when not in external master mode, otherwise used by external master. Note: PerData0 is the most significant bit (msb) on this bus. Peripheral address bus used by PPC405GPr when not in external master mode, otherwise used by external master. Note: PerAddr0 is the most significant bit (msb) on this bus. Peripheral byte parity signals. As outputs, these pins can act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. As outputs, pins are used by either the pripheral controller or the DMA controller depending upon the type of transfer involved. Used as inputs when an external bus master owns the external interface. Peripheral write enable. Low when any of the four PerWBE0:3 write byte enables are low. or PCI interrupt. Open-drain output (two states; 0 or open circuit) I/O 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
PerAddr0:31
I/O
1
PerPar0:3
I/O
1
PerWBE0:3
I/O
5V tolerant 3.3V LVTTL
1, 7
[PerWE]PCIINT
O
5V tolerant 3.3V PCI
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405GPr - Power PC 405GPr Embedded Processor
Data Sheet
Signal Functional Description
(Sheet 4 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name PerCS0 Description Peripheral chip select bank 0. Seven additional peripheral chip selects or General Purpose I/O. To access this function, software must toggle a DCR bit. Used by either the peripheral controller or the DMA controller depending upon the type of transfer involved. When the PPC405GPr is the bus master, it enables the selected device to drive the bus. Used by the PPC405GPr when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise it used by the external master as an input to indicate the direction of data transfer. Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC405GPr when not in external master mode, otherwise used by external master. Indicates the last transfer of a memory access. DMAReq0:3 are used by slave peripherals to indicate they are prepared to transfer data. DMAAck0:3 are used by the PPC405GPr to cause the DMA peripheral to transfer data. End Of Transfer/Terminal Count. I/O O Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
7
PerCS1:7[GPIO10:16]
O[I/O]
1, 7
PerOE
O
5V tolerant 3.3V LVTTL
7
PerR/W
I/O
5V tolerant 3.3V LVTTL
1
PerReady
I
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
1
PerBLast
I/O
1, 7
DMAReq0:3 DMAAck0:3 EOT0:3/TC0:3
I O I/O
1 6 1
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405GPr - Power PC 405GPr Embedded Processor
Revision 2.04 - September 7, 2007
Data Sheet
Signal Functional Description
(Sheet 5 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description I/O Type
Notes
External Master Peripheral Interface
PerClk ExtReset HoldReq HoldAck ExtReq ExtAck HoldPri BusReq PerErr Peripheral clock to be used by an external master and by synchronous peripheral slaves. Peripheral reset to be used by an external master and by synchronous peripheral slaves. Hold Request, used by an external master to request ownership of the peripheral bus. Hold Acknowledge, used by the PPC405GPr to transfer ownership of peripheral bus to an external master. ExtReq is used by an external master to indicate it is prepared to transfer data. ExtAck is used by the PPC405GPr to indicate a data transfer cycle. Used by an external master to indicate the priority of a given external master tenure. Used when the PPC405GPr needs to regain control of peripheral interface from an external master. An input used to indicate to the PPC405GPr that an external slave peripheral error occurred. O O I O I O I O I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 5 1, 5 6 1 6 1
Internal Peripheral Interface
UARTSerClk Serial Clock used to provide an alternate clock to the internally generated serial clock. Used in cases where the allowable internally generated baud rates are not satisfactory. This input can be individually connected to either UART. UART0 Serial Data In. UART0 Serial Data Out. UART0 Data Carrier Detect. UART0 Data Set Ready. UART0 Clear To Send. UART0 Data Terminal Ready. UART0 Request To Send. UART0 Ring Indicator. UART1 Serial Data In. I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1
UART0_Rx UART0_Tx UART0_DCD UART0_DSR UART0_CTS UART0_DTR UART0_RTS UART0_RI UART1_Rx
I O I I I O O I I
1 6 1 1 1 6 6 1 1
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405GPr - Power PC 405GPr Embedded Processor
Data Sheet
Signal Functional Description
(Sheet 6 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name UART1_Tx UART1 Serial Data Out. UART1 Data Set Ready or UART1 Clear To Send. To access this function, software must toggle a DCR bit. UART1 Request To Send or UART1 Data Terminal Ready. To access this function, software must toggle a DCR bit. IIC Serial Clock. IIC Serial Data. Description I/O O Type 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
Notes
6
UART1_DSR/ UART1_CTS
I
1
UART1_RTS/ UART1_DTR
O
5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
6
IICSCL IICSDA
I/O I/O
1, 2 1, 2
Interrupts Interface
Interrupt requests or General Purpose I/O. To access this function, software must toggle a DCR bit. 5V tolerant 3.3V LVTTL
IRQ0:6[GPIO17:23]
I[I/O]
1
JTAG Interface
TDI TMS TDO TCK TRST Test data in. JTAG test mode select. Test data out. JTAG test clock. The frequency of this input can range from DC to 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405GPr. I I O I I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 4 5 1, 4 1, 4
System Interface
SysClk Main system clock input. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an open-drain output (two states; 0 or open circuit). Clean voltage input for the PLL. Clean Ground input for the PLL. Set to 1 when a Machine Check is generated. Halt from external debugger. I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL
SysReset
I/O
1, 2
AVDD AGND SysErr Halt
I I O I 5V tolerant 3.3V LVTTL 5V tolerant 3.3V LVTTL 1, 2
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405GPr - Power PC 405GPr Embedded Processor
Revision 2.04 - September 7, 2007
Data Sheet
Signal Functional Description
(Sheet 7 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name GPIO1[TS1E] GPIO2[TS2E] Description General Purpose I/O or Even Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I/O or Odd Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I/O or Odd Trace execution status. To access this function, software must toggle a DCR bit. General Purpose I/O or Trace status. To access this function, software must toggle a DCR bit. General Purpose I/O or Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit. Note: Initialization strapping must hold this pin low (0) during reset. General Purpose I/O. Note: The pull-up initialization strapping resistor must be 1k rather than 3k in order to overcome the internal pull-down resistor. Test Enable. Used only for manufacturing tests. Pull down for normal operation. An external clock input that can be used to clock the timers in the CPU core. I/O Type 5V tolerant 3.3V LVTTL
Notes
I/O[O]
1, 6
GPIO3[TS1O]
I/O[O]
5V tolerant 3.3V LVTTL
1, 6
GPIO4[TS2O]
I/O[O]
5V tolerant 3.3V LVTTL
1, 6
GPIO5:8[TS3:6]
I/O[O]
5V tolerant 3.3V LVTTL
1, 6
GPIO9[TrcClk]
I/O[O]
5V tolerant 3.3V LVTTL
1, 6
GPIO24
I/O
3.3V LVTTL w/pull-down 1.8V CMOS w/pull-down 5V tolerant 3.3V LVTTL
1, 6
TestEn TmrClk
I I
1
Trace Interface
[TS1E]GPIO1 [TS2E]GPIO2 Even Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I/O. Odd Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I/O. Odd Trace execution status. To access this function, software must toggle a DCR bit or General Purpose I/O. 5V tolerant 3.3V LVTTL
O[I/O]
1, 6
[TS1O]GPIO3
O[I/O]
5V tolerant 3.3V LVTTL
1, 6
[TS2O]GPIO4
O[I/O]
5V tolerant 3.3V LVTTL
1, 6
[TS3:6]GPIO5:8
Trace status. To access this function, software must toggle a DCR bit or O[I/O] General Purpose I/O.
5V tolerant 3.3V LVTTL
1, 6
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Revision 2.04 - September 7, 2007
405GPr - Power PC 405GPr Embedded Processor
Data Sheet
Signal Functional Description
(Sheet 8 of 8) Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 3. Must pull down. See "Pull-Up and Pull-Down Resistors" on page 29 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See "External Bus Control Signals" on page 29.
Signal Name Description Trace interface clock. A toggling signal that is always half of the CPU core frequency. To access this function, software must toggle a DCR bit or General Purpose I/O. Note: Initialization strapping must hold this pin low (0) during reset. I/O Type
Notes
[TrcClk]GPIO9
O[I/O]
5V tolerant 3.3V LVTTL
1, 6
Ground pins
GND Ground Note: L11-L16, M11-M16, N11-N16, P11-P16, R11-R16, and T11-T16 are also thermal balls.
OVDD pins
OVDD Output driver voltage--3.3V.
VDD pins
VDD Logic voltage--1.8V.
Other pins
Reserved Reserved--Except for AF4, do not connect signals, voltage, or ground to these pins. AF4 must be tied to OVDD or GND.
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405GPr - Power PC 405GPr Embedded Processor
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Data Sheet
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device
Characteristic Supply Voltage (Internal Logic) Supply Voltage (I/O Interface) PLL Supply Voltage Input Voltage (1.8V CMOS receivers) Input Voltage (3.3V LVTTL receivers) Input Voltage (5.0V LVTTL receivers) Storage Temperature Range Case temperature under bias Notes: 1. All specified voltages are with respect to GND. 2. Empirical data indicates that all chip voltages should begin to ramp-up within 1 ms of each other. There should never be voltage present at the I/O pins before OVDD is within operating range. Symbol VDD OVDD AVDD VIN VIN VIN TSTG TC Value 0 to +1.95 0 to +3.6 0 to +1.95 -0.6 to VDD + 0.45 -0.6 to OVDD + 0.6 -0.6 to OVDD + 2.4 -55 to +150 -40 to +120 Unit V V V V V V C C
Package Thermal Specifications
The PPC405GPr is designed to operate within a case temperature range of -40C to +85C3. Thermal resistance values for the E-PBGA packages (leaded and lead-free) in a convection environment are as follows: Airflow ft/min (m/sec) Symbol Unit Package--Thermal Resistance
0 (0) 35mm, 456-balls--Junction-to-Case 35mm, 456-balls--Case-to-Ambient1 27mm, 456-balls--Junction-to-Case 27mm, 456-balls--Case-to-Ambient1 Notes: 1. For a chip mounted on a JEDEC 2S2P card without a heat sink. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. b. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. c. TCMax = TJMax - PxJC, where TJMax is maximum junction temperature and P is power consumption. 3. 333MHz operated at 266MHz or less can operate at +105C. 100 (0.51) 2 13 2 16 200 (1.02) 2 12 2 15 C/W C/W C/W C/W
JC CA JC CA
2 14 2 18
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405GPr - Power PC 405GPr Embedded Processor
Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Notes: 1. PCI drivers meet PCI specifications. 2. See "5V-Tolerant Input Current" on page 40. 3. 333MHz operated at 266MHz or less can operate at +105C.
Parameter Logic Supply Voltage (266 &333MHz) Logic Supply Voltage (400MHz) I/O Supply Voltage PLL Supply Voltage Input Logic High (1.8V CMOS receivers) Input Logic High (3.3V LVTTL receivers) Input Logic High (5.0V LVTTL receivers) Input Logic Low (1.8V CMOS receivers) Input Logic Low (3.3/5.0V LVTTL receivers) Output Logic High Output Logic Low 3.3V I/O Input Current (no pull-up or pull-down) Input Current (with internal pull-down) 5V Tolerant I/O Input Current Input Max Allowable Overshoot (1.8V CMOS receivers) Input Max Allowable Overshoot (3.3V LVTTL receivers) Input Max Allowable Overshoot (5.0V LVTTL receivers) Input Max Allowable Undershoot Output Max Allowable Overshoot Output Max Allowable Undershoot Case Temperature Symbol VDD VDD OVDD AVDD VIH VIH VIH VIL VIL VOH VOL IIL1 IIL2 IIL4 VIMAO1.8 VIMAO3 VIMAO5 VIMAU VOMAO VOMAU3 TC -0.6 -40 +85 -0.6 OVDD + 0.3 10 (@ 0V) 10 Minimum 1.7 1.8 3.0 1.7 0.65VDD 2.0 2.0 0 0 2.4 0 Typical 1.8 1.85 3.3 1.8 Maximum 1.9 1.9 3.6 1.9 VDD OVDD 5.0 0.65VDD 0.8 OVDD 0.4 10 200 (@ VDD) -325 VDD + 0.6 OVDD + 0.6 5.5 Unit V V V V V V V V V V V Notes
A A A
V V V V V V C 3 2
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405GPr - Power PC 405GPr Embedded Processor
Revision 2.04 - September 7, 2007
Data Sheet
5V-Tolerant Input Current
50 0 -50 Input Current (A) -100 -150 -200 -250 -300 -350 0.0 1.0 2.0 3.0 4.0 5.0 Input Voltage (V)
Input Capacitance
Parameter 3.3V LVTTL I/O 5V tolerant LVTTL I/O PCI I/O Rx only pins Symbol CIN1 CIN2 CIN3 CIN4 Maximum 8.8 8 9.3 4.5 Unit pF pF pF pF Notes
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Revision 2.04 - September 7, 2007
405GPr - Power PC 405GPr Embedded Processor
Data Sheet
DC Electrical Characteristics
Parameter Active Operating Current (VDD)-266MHz Active Operating Current (VDD)-333MHz Active Operating Current (VDD)-400MHz Active Operating Current (OVDD) PLL VDD Input current Active Operating Power-266 MHz Active Operating Power-333MHz Active Operating Power-400MHz Note: 1. The maximum current and power values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OVDD (I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses. The following information provides details about the conditions under which the listed values were obtained: a. In general, the values were measured using a PPC405GPr Evaluation Board with four PCI devices, an external bus master on the peripheral bus, and external wrap-back on the Ethernet port. For all CPU clock rates, PLB = 133.3MHz, OPB = PerClk = 66.6MHz, PCI = SysClk = 33.3MHz. b. Typical current and power are characterized at VDD = +1.8V, OVDD = +3.3V, and TC = +36C while running various applications under the Linux operating system. c. Maximum current and power are characterized at VDD = +1.9V, OVDD = +3.6V, and TC = +85C while running applications designed to maximize CPU power consumption. An external PCI master heavily loads the PCI bus with transfers targeting SDRAM while the internal DMA controller further increases SDRAM bus traffic. 2. AVDD should be derived from VDD using the following circuit: Symbol IDD IDD IDD IODD IPLL PDD PDD PDD Typical 300 325 355 45 16 0.72 0.76 0.82 Maximum 610 690 770 200 23 1.92 2.07 2.23 Unit mA mA mA mA mA W W W
VDD L1
AVDD
+ C1 C2 C3
AGND GND
L1 - 2.2H SMT inductor (equivalent to MuRata LQH3C2R2M34) or SMT chip ferrite bead (equivalent to MuRata BLM31A700S) C1 - 3.3 F SMT tantalum C2 - 0.1F SMT monolithic ceramic capacitor with X7R dielectric or equivalent C3 - 0.01 F SMT monolithic ceramic capacitor with X7R dielectric or equivalent
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405GPr - Power PC 405GPr Embedded Processor
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Data Sheet
Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in the table "Recommended DC Operating Conditions." For all signals other than PCI signals, AC specifications are characterized at OVDD = +3V and TC = +85C with the 50pF test load shown in the figure at right. For PCI signals there are two different test load circuits, one for the rising edge and one the falling edge as shown in the figures at right.
Output Pin
50pF
All signals other than PCI
Output Pin
PCI Rising edge
10pF
25
Output Pin
25 10pF
OVDD
PCI Falling edge
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Data Sheet
Clocking Specifications
Symbol CPU PFC PTC SysClk Input SCFC SCTC SCTCS SCTCH SCTCL Clock input frequency Clock period Clock edge stability (phase jitter, cycle to cycle) Clock input high time Clock input low time 40% of nominal period 40% of nominal period 25 15 66.66 40 0.15 60% of nominal period 60% of nominal period MHz ns ns ns ns Processor clock frequency Processor clock period 3.75/3/2.5 266.66/333.33/400 MHz ns Parameter Min Max Units
Note: Input slew rate > 1V/ns between 0.8V and 2.0V MemClkOut Output MCOFC MCOTC MCOTCS MCOTCH MCOTCL TrcClk Output TCFC TCTC TCTCS TCTCH TCTCL Other Clocks VCOFC VCOFC PLBFC OPBFC VCO frequency VCO frequency @ PFC = 333MHz or 400MHz PLB frequency OPB frequency 500 500 1000 1333 133.33 66.66 MHz MHz MHz MHz Clock output frequency Clock period Clock edge stability (phase jitter, cycle to cycle) Clock output high time Clock output low time 45% of nominal period 45% of nominal period PFC / 2 PTC x 2 0.2 55% of nominal period 55% of nominal period MHz ns ns ns ns Clock output frequency @ PFC = 266MHz Clock period @ PFC = 266MHz Clock edge stability (phase jitter, cycle to cycle) Clock output high time Clock output low time 45% of nominal period 45% of nominal period 7.5 0.2 55% of nominal period 55% of nominal period 133.33 MHz ns ns ns ns
Clocking Waveform
2.0V 1.5V 0.8V TCH TC TCL
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Data Sheet
Spread Spectrum Clocking
Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC405GPr. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC405GPr the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC405GPr with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. * The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC405GPr peripherals impose more stringent requirements (see Note 1). * Use the peripheral bus clock (PerClk) for logic that is synchronous to the peripheral bus since this clock tracks the modulation. * Use the SDRAM MemClkOut since it also tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. If an external serial clock is used the baud rate is unaffected by the modulation. 2. Operation of the PPC405GPr PCI Bridge is unaffected by the use of a SSCG. For PCI frequencies of 33.33 MHz and below the PCI controller supports synchronous mode operation. This is accomplished by strapping the PPC405GPr for synchronous mode PCI and connecting the PCI bus clock to the PPC405GPr SysClk input. For 33.33 MHz signalling, the PCI specification has no limitation on the amount of frequency deviation or modulation that may be applied to the PCI clock. Therefore, the PPC405GPr SSCG requirements stated above take precedence. At PCI frequencies above 33.33 MHz, the PCI controller must be operated in asynchronous mode. When in asynchronous mode, the PCI bus clock must be driven into the PPC405GPr PCIClk input. In this configuration the PCI controller supports the 66.66 MHz PCI clock specification which specifies a maximum frequency deviation of -1% at a modulation of between 30 kHz and 33 kHz. 3. Ethernet operation is unaffected. 4. IIC operation is unaffected. Caution: It is up to the system designer to ensure that any SSCG used with the PPC405GPr meets the above requirements and does not adversely affect other aspects of the system.
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Data Sheet
Peripheral Interface Clock Timings
Parameter PCIClk input frequency (asynchronous mode) PCIClk period (asynchronous mode) PCI Clock frequency (synchronous mode) PCI Clock period (synchronous mode - Note 2) PCIClk input high time PCIClk input low time EMCMDClk output frequency EMCMDClk period EMCMDClk output high time EMCMDClk output low time PHYTxClk input frequency PHYTxClk period PHYTxClk input high time PHYTxClk input low time PHYRxClk input frequency PHYRxClk period PHYRxClk input high time PHYRxClk input low time PerClk output frequency PerClk period PerClk output high time PerClk output low time PerClk clock edge stability (phase jitter, cycle to cycle) UARTSerClk input frequency (Note 3) UARTSerClk period UARTSerClk input high time UARTSerClk input low time TmrClk input frequency TmrClk period TmrClk input high time TmrClk input low time Note: 1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GPr Embedded Processor User's Manual for more information. 2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused. 3. TOPB is the period in ns of the OPB clock. The maximum OPB clock frequency is 66.66MHz. - 2TOPB+2 TOPB+1 TOPB+1 - 15 40% of nominal period 40% of nominal period Min Note 1 15 25 30 40% of nominal period 40% of nominal period - 400 160 160 2.5 40 35% of nominal period 35% of nominal period 2.5 40 35% of nominal period 35% of nominal period - 15 45% of nominal period 45% of nominal period Max 66.66 Note 1 33.33 40 60% of nominal period 60% of nominal period 2.5 - - - 25 400 - - 25 400 - - 66.66 - 55% of nominal period 55% of nominal period 0.3 1000/(2TOPB+2ns) - - - 66.66 - 60% of nominal period 60% of nominal period Units MHz ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns ns MHz ns ns ns MHz ns ns ns
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Data Sheet
Input Setup and Hold Waveform
Clock
TIS min Inputs Valid
TIH min
Output Delay and Float Timing Waveform
Clock
TOV max Outputs TOH min
TOV max TOH min
TOV max TOH min
High (Drive) Float (High-Z) Low (Drive) Valid Valid
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Data Sheet
Notes: 1. In all of the following I/O Specifications tables a timing values of "na" means "not applicable" and "dc" means "don't care." 2. See "Test Conditions" on page 42 for output capacitive loading.
I/O Specifications--Group 1
(Sheet 1 of 3) Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) 3 3 dc 3 3 na 3 na 3 3 3 5 na na 3 3 na 100 na na na Hold Time (TIH min) 0 0 dc 0 0 na 0 na 0 0 0 0 na na 0 0 na 0 na na na Output (ns) Valid Delay (TOV max) 6 6 na 6 6 na 6 dc 6 6 6 na na na 6 6 settable 1 OPB clock period + 10ns 20 20 20 Hold Time (TOH min) 1 1 na 1 1 na 1 dc 1 1 1 na na na 1 1 2 1 OPB clock period 2 2 2 Output Current (mA) I/O H (min) 0.5 0.5 na 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 na 0.5 0.5 0.5 0.5 10.3 10.3 10.3 10.3 10.3 10.3 10.3 na 4 4 4 1 1 1 na na na na na na 10.3 10.3 10.3 na I/O L (min) 1.5 1.5 na 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 na 1.5 1.5 1.5 1.5 7.1 7.1 7.1 7.1 7.1 7.1 7.1 na 7.1 7.1 7.1 na PHYRX PHYRX PHYRX EMCMDClk PHYTX PHYTX PHYTX PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock PCI Clock 1 1 2, async 2 2 2 2 2, async 2, async 2, async 2 2 2 2, async Clock Notes
PCI Interface
PCIAD31:0 PCIC3:0[BE3:0] PCIClk PCIDevSel PCIFrame PCIGnt0[Req] PCIGnt1:5 PCIIDSel PCIINT[PerWE] PCIIRDY PCIParity PCIPErr PCIReq0[Gnt] PCIReq1:5 PCIReset PCISErr PCIStop PCITRDY PCI Clock PCI Clock 1 1 async 1 1 1 1 async 1 1 1 1
Ethernet Interface
EMCMDClk EMCMDIO[PHYMDIO] EMCTxD3:0 EMCTxEn EMCTxErr PHYCol PHYCrS PHYRxClk PHYRxD3:0 PHYRxDV PHYRxErr PHYTxClk
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Data Sheet
I/O Specifications--Group 1
(Sheet 2 of 3) Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na na Hold Time (TIH min) na na na na na na na na na na na na na na na na na na na na na Output (ns) Valid Delay (TOV max) na na Hold Time (TOH min) na na Output Current (mA) I/O H (min) 15.3 15.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 10.3 na na 10.3 na 10.3 na na 10.3 na na I/O L (min) 10.2 10.2 7.1 7.1 7.1 7.1 7.1 7.1 7.1 7.1 7.1 na na 7.1 na 7.1 na na 7.1 na na async async async async async Clock Notes
Internal Peripheral Interface
IICSCL IICSDA UART0_CTS UART0_DCD UART0_DSR UART0_DTR UART0_RI UART0_RTS UART0_Rx UART0_Tx UART1_RTS/ UART1_DTR UART1_DSR/ UART1_CTS UART1_Rx UART1_Tx UARTSerClk
Interrupts Interface
IRQ0:6[GPIO17:23]
JTAG Interface
TCK TDI TDO TMS TRST
System Interface
GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO24 Halt SysClk SysErr SysReset TestEn TmrClk dc dc dc dc dc dc na na na 10 na na na na na 1 na na
10.3
7.1
na na 10.3 10.3 na na
na na 7.1 7.1 na na
async async async async async
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Data Sheet
I/O Specifications--Group 1
(Sheet 3 of 3) Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Trace [TS1E] [TS2E] [TS1O] [TS2O] [TS3] [TS4] [TS5] [TS6] Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (min) I/O L (min) Clock Notes
na
na
PTC/2+0.7
PTC/2-0.5
10.3
7.1
TrcClk
10pF load on clk/data
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Data Sheet
I/O Specifications--Group 2
Notes: 1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the command is used by SDRAM. 2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load. 3. SDRAM interface hold times are guaranteed at the PPC405GPr package pin. System designers must use the PPC405GPr IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections, and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring. 4. PerClk timing is specified with a 10pF load at the package pin. The indicated timing is valid only if PerClk feedback is selected. Refer to the PowerPC 405GPr Embedded Processor User's Manual for more information. 5. Input timings are specified at 1.5V, assuming transition times between 1 and 2ns, when measured between the 10% and 90% points of the output voltage. 6. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
Input (ns) Signal Setup Time (TIS min) na na na na na na 1.4 na 1.4 na na na 3.2 dc 2.2 3.3 na 4.7 na 2.3 3.3 5.5 2.3 na na 4.1 na na 2.1 3.1 na 2.4 Hold Time (TIH min) na na na na na na 0 na 0 na na na 0 dc 0 0 na 0.9 na 0 0 0 0 na na 0 na na 0 0 na 0 Output (ns) Valid Delay (TOV max) 4.5 4.5 4.4 3.9 4.5 4.3 4.5 4.6 5.1 4.4 4.4 6.1 na 6.4 7.1 6.5 6.5 7.2 6.5 7.2 6.6 na 6.1 6.1 5.9 na 6 6.1 na na 0.7 na Hold Time (TOH min) 1.6 1.5 1.5 1.4 1.4 1.4 1.5 1.5 1.4 1.5 1.5 2.2 na 2 2 2.3 2.1 1.9 2.1 2.1 2.1 na 2.2 2.2 2.1 na 1 2 na na -0.5 na Output Current (mA) I/O H (minimum) 15.3 15.3 15.3 23 15.3 15.3 15.3 15.3 15.3 15.3 15.3 10.3 na 10.3 15.3 10.3 10.3 15.3 10.3 15.3 10.3 na 10.3 10.3 10.3 na 15.3 10.3 na na 15.3 na I/O L (minimum) 10.2 10.2 10.2 19.3 10.2 10.2 10.2 10.2 10.2 10.2 10.2 7.1 na 7.1 10.2 7.1 7.1 10.2 7.1 10.2 7.1 na 7.1 7.1 7.1 na 10.2 7.1 na na 10.2 na Clock Notes
SDRAM Interface
BA1:0 BankSel3:0 CAS ClkEn0:1 DQM0:3 DQMCB ECC0:7 MemAddr12:0 MemData0:31 RAS WE DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr0:31 PerBLast PerCS0 PerCS1:7[GPIO10:16] PerData0:31 PerOE PerPar0:3 PerR/W PerReady PerWBE0:3 BusReq ExtAck ExtReq ExtReset HoldAck HoldPri HoldReq PerClk PerErr MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut MemClkOut PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk SysClk PerClk 1, 2, 5 2, 5 1, 2, 5 2, 5 2, 5 2, 5 2, 5 1, 2, 5 2, 5 1, 2, 5 1, 2, 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 4, 5 5
External Slave Peripheral Interface
External Master Peripheral Interface
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Data Sheet
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to enable default initial conditions prior to PPC405GPr start-up. The actual capture instant is the nearest SysClk edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. The recommended pull-up is 3k to +3.3V or 10k to +5V. The recommended pull-down is 1K to GND. These pins are use for strap functions only during reset. They are used for other signals during normal operation. The following tables list the strapping pins along with their functions and strapping options. The signal names assigned to the pins for normal operation follow the pin number. The PPC405GPr can be used as a replacement for the PPC405GP. When the PPC405GPr is used for this purpose, it should be strapped to operate in the PPC405GPr Legacy Mode. This option is selected by strapping ball D20 (GPIO24) low (0). If Legacy Mode is selected, the "PPC405GPr Legacy Mode Strapping Pin Assignments" table should be used to determine the strapping options. To operate the chip as a PPC405GPr, strap D20 (GPIO24) high (1) and use "PPC405GPr New Mode Strapping Pin Assignments" on page 53 to determine the strapping options.
PPC405GPr Legacy Mode Strapping Pin Assignments
Function PLL Tuning
1
(Sheet 1 of 2)
Ball Strapping AF3 UART0_Tx AF2 UART0_DTR 0 0 1 1 0 0 1 1 B15 DMAAck1 0 1 0 1 C12 DMAAck3 0 1 0 1 L24 EMCTxD2 0 1 0 1 AD16 UART0_RTS 0 1 0 1 0 1 0 1
Option
for 6 M 7 use choice 3 for 7 < M 12 use choice 5 for 12 < M 32 use choice 6 Choice 1; TUNE[9:0] = 1010111100 Choice 2; TUNE[9:0] = 0100111000 Choice 3; TUNE[9:0] = 0100110110 Choice 4; TUNE[9:0] = 0100111100 Choice 5; TUNE[9:0] = 0100111000 Choice 6; TUNE[9:0] = 1000111100 Choice 7; TUNE[9:0] = 1000111110 Choice 8; TUNE[9:0] = 1011111110 PLL Forward Divider
2
0 0 0 0 1 1 1 1 D16 DMAAck0
Bypass mode Divide by 3 Divide by 4 Divide by 6 PLL Feedback Divider
2
0 0 1 1 B14 DMAAck2
Divide by 1 Divide by 2 Divide by 3 Divide by 4 PLB Divider from CPU
2
0 0 1 1 P25 EMCTxD3
Divide by 1 Divide by 2 Divide by 3 Divide by 4
0 0 1 1
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Data Sheet
PPC405GPr Legacy Mode Strapping Pin Assignments
Function OPB Divider from PLB 2 Divide by 1 Divide by 2 Divide by 3 Divide by 4 PCI Divider from PLB 2, 3 Divide by 1 Divide by 2 Divide by 3 Divide by 4 External Bus Divider from PLB
2
(Sheet 2 of 2)
Ball Strapping L25 EMCTxD1 0 0 1 1 D18 GPIO1[TS1E] 0 0 1 1 K25 EMCTxErr J26 EMCTxD0 0 1 0 1 C20 GPIO2[TS2E] 0 1 0 1 K23 EMCTxEn 0 1 0 1 AD2 UART1_RTS/ UART1_DTR 0 1 0 1
Option
Divide by 2 Divide by 3 Divide by 4 Divide by 5 ROM Width
0 0 1 1 AC2 UART1_Tx
8-bit ROM 16-bit ROM 32-bit ROM Reserved ROM Location PPC405GPr Peripheral Attach PPC405GPr PCI Attach PCI Asynchronous Mode Enable Synchronous PCI Mode Asynchronous Mode PCI Arbiter Enable 3 Internal Arbiter Disabled Internal Arbiter Enabled Note:
0 0 1 1 U2 HoldAck 0 1 Y3 ExtAck 0 1 AF18 GPIO4[TS2O] 0 1
1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr, visit the technical documents area of the AMCC PowerPC web site. 2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in "Clocking Specifications" on page 43. Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded Processor User's Manual. 3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs.
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Data Sheet
PPC405GPr New Mode Strapping Pin Assignments
Function PLL Tuning See the PowerPC 405GPr Embedded Processor User's Manual for details. Option AF3 UART0_Tx Choice 1; TUNE[9:0] = 1010111100 Choice 2; TUNE[9:0] = 0100111000 Choice 3; TUNE[9:0] = 0100110110 Choice 4; TUNE[9:0] = 0100111100 Choice 5; TUNE[9:0] = 0100111000 Choice 6; TUNE[9:0] = 1000111100 Choice 7; TUNE[9:0] = 1000111110 Choice 8; TUNE[9:0] = 1011111110 PLL Forward Divider A 2 Divide by 8 Divide by 7 Divide by 6 Divide by 5 Divide by 4 Divide by 3 Divide by 2 Divide by 1 PLL Forward Divider B
2
(Sheet 1 of 3)
Ball Strapping AF2 UART0_DTR 0 0 1 1 0 0 1 1 B15 DMAAck1 0 0 1 1 0 0 1 1 L24 EMCTxD2 0 0 1 1 0 0 1 1 AD16 UART0_RTS 0 1 0 1 0 1 0 1 AC9 GPIO5[TS3] 0 1 0 1 0 1 0 1 AE8 GPIO6[TS4] 0 1 0 1 0 1 0 1
0 0 0 0 1 1 1 1 D16 DMAAck0 0 0 0 0 1 1 1 1 P25 EMCTxD3
Divide by 8 Divide by 7 Divide by 6 Divide by 5 Divide by 4 Divide by 3 Divide by 2 Divide by 1
0 0 0 0 1 1 1 1
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Data Sheet
PPC405GPr New Mode Strapping Pin Assignments
Function PLL Feedback Divider 2, 3 Divide by 16 Divide by 1 Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 Divide by 7 Divide by 8 Divide by 9 Divide by 10 Divide by 11 Divide by 12 Divide by 13 Divide by 14 Divide by 15 OPB Divider from PLB
2
(Sheet 2 of 3)
Ball Strapping C12 DMAAck3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 J26 EMCTxD0 0 1 0 1 C20 GPIO2[TS2E] 0 1 0 1 K23 EMCTxEn 0 1 0 1 AD2 UART1_RTS/ UART1_DTR 0 1 0 1 AF5 GPIO7[TS5] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 AC7 GPIO8[TS6] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Option B14 DMAAck2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 L25 EMCTxD1 Divide by 1 Divide by 2 Divide by 3 Divide by 4
2, 3
0 0 1 1 D18 GPIO1[TS1E]
PCI Divider from PLB
Divide by 1 Divide by 2 Divide by 3 Divide by 4 External Bus Divider from PLB 2 Divide by 2 Divide by 3 Divide by 4 Divide by 5 ROM Width
0 0 1 1 K25 EMCTxErr 0 0 1 1 AC2 UART1_Tx
8-bit ROM 16-bit ROM 32-bit ROM Reserved ROM Location PPC405GPr Peripheral Attach PPC405GPr PCI Attach
0 0 1 1 U2 HoldAck 0 1
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Data Sheet
PPC405GPr New Mode Strapping Pin Assignments
Function PCI Asynchronous Mode Enable Synchronous PCI Mode Asynchronous Mode External Bus Synchronous Mode Enable 3 Asynchronous Mode Synchronous Mode PCI Arbiter Enable 3 Internal Arbiter Disabled Internal Arbiter Enabled New Mode Enable In Legacy mode the PPC405GPr functions like the PPC405GP. If not strapped, the PPC405GPr defaults to Legacy mode. Flip Circuit Disable (must be strapped low (0) during initilization). Note: 1. The tune bits adjust parameters that control PLL jitter. The recommended values minimize jitter for the PLL implemented in the PPC405GPr. These bits are shown for information only; and do not require modification except in special clocking circumstances such as spread spectrum clocking. For details on the use of Spread Spectrum Clock Generators (SSCGs) with the PPC405GPr, visit the technical documents area of the AMCC PowerPC web site. 2. Not all combinations of dividers produce valid operating configurations. Frequencies must be within the limits specified in "Clocking Specifications" on page 43. Further requirements are detailed in the Clocking chapter of the PowerPC 405GPr Embedded Processor User's Manual. 3. Additional consideration must be given to pins that normally function as Trace signals. Improved design margin can be gained by using three-state buffers instead of strapping resistors, and minimizing trace lengths and stubs. 4. The pull-up initialization strapping resistor must be 1k rather than 3k in order to overcome the internal pull-down resistor. Option Y3 ExtAck 0 1 A22 GPIO3[TS1O] 0 1 AF18 GPIO4[TS2O] 0 1 D20 GPIO24 Legacy (PPC405GP) mode New (PPC405GPr) mode4 0 1 AB3 GPIO9[TrcClk] Normal operation 0
(Sheet 3 of 3)
Ball Strapping
Revision Log
Date 03/13/2003 08/28/2003 11/22/2004 12/02/2004 01/06/2005 08/29/2005 03/13/2007 09/07/2007 Add new VDD values for 400MHz parts. Correct package drawings and add lead-free part numbers. Add +105C temperature specification. Add 1 ms. voltage ramp-up restriction. Update to AMCC format. Correct typographical error in 27mm package drawing. Add dashes back into PNs. Revise package drawings to add logo view. Update AMCC address and copyright date on last page. Change TestEn signal from active low to active high. Correct AMCC telephone numbers. Contents of Modification 400MHz part numbers and new power/current numbers
AMCC
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Data Sheet
Printed in the United States of America, Friday, September 07, 2007 The following are trademarks of AMCC in the United States, or other countries, or both: AMCC
Other company, product, and service names may be trademarks or service marks of others.
The information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or implied, including without limitation, the implied warranties of non-infringement, merchantability, or fitness for a particular purpose. Any products, services, or programs discussed in this document are sold or licensed under AMCC's standard terms and conditions, copies of which may be obtained from your local AMCC representative. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of AMCC or third parties. Without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal AMCC test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein.
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Data Sheet
Applied Micro Circuits Corporation 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (408) 542-8600 -- (800) 840-6055 -- Fax: (408) 542-8601 http://www.amcc.com
AMCC reserves the right to make changes to its products, its datasheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available datasheet. Please consult AMCC's Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright (c) 2007 Applied Micro Circuits Corporation.
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